View M464S1724CT1-L1LC1L_1269637.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

M464S1724CT1
M464S1724CT1 SDRAM SODIMM
PC100 SODIMM
16Mx64 SDRAM SODIMM based on 8Mx16,4Banks,4K Refresh,3.3V Synchronous DRAMs with SPD GENERAL DESCRIPTION
The Samsung M464S1724CT1 is a 16M bit x 64 Synchronous Dynamic RAM high density memory module. The Samsung M464S1724CT1 consists of eight CMOS 8M x 16 bit with 4banks Synchronous DRAMs in TSOP-II 400mil package and a 2K EEPROM in 8-pin TSSOP package on a 144-pin glass-epoxy substrate. Three 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The M464S1724CT1 is a Small Outline Dual In-line Memory Module and is intended for mounting into 144-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications.
FEATURE
* Performance range Part No. M464S1724CT1-L1H/C1H M464S1724CT1-L1L/C1L * * * * * Max Freq. (Speed) 100MHz (10ns @ CL=2) 100MHz (10ns @ CL=3)
Burst mode operation Auto & self refresh capability (4096 Cycles/64ms) LVTTL compatible inputs and outputs Single 3.3V 0.3V power supply MRS cycle with address key programs Latency (Access from column address) Burst length (1, 2, 4, 8 & Full page) Data scramble (Sequential & Interleave) * All inputs are sampled at the positive going edge of the system clock * Serial presence detect with EEPROM * PCB : Height (1,250mil) , double sided component
PIN CONFIGURATIONS (Front side/back side)
Pin Front Pin 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 VSS DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 VSS DQM0 DQM1 VDD A0 A1 A2 VSS DQ8 DQ9 DQ10 DQ11 VDD DQ12 DQ13 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 Back VSS DQ32 DQ33 DQ34 DQ35 VDD DQ36 DQ37 DQ38 DQ39 VSS DQM4 DQM5 VDD A3 A4 A5 VSS DQ40 DQ41 DQ42 DQ43 VDD DQ44 DQ45 Pin Front 51 53 55 57 59 DQ14 DQ15 VSS NC NC Pin 52 54 56 58 60 Back Pin Front DQ21 DQ22 DQ23 VDD A6 A8 VSS A9 A10/AP VDD DQM2 DQM3 VSS DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 VSS **SDA VDD Pin 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 Back DQ53 DQ54 DQ55 VDD A7 BA0 VSS BA1 A11 VDD DQM6 DQM7 VSS DQ56 DQ57 DQ58 DQ59 VDD DQ60 DQ61 DQ62 DQ63 VSS **SCL VDD DQ46 95 DQ47 97 VSS 99 NC 101 NC 103 105 107 Voltage Key 109 CLK0 62 CKE0 111 VDD 64 VDD 113 RAS 66 CAS 115 WE 68 CKE1 117 CS0 70 *A12 119 CS1 72 *A13 121 DU 74 CLK1 123 VSS 76 VSS 125 NC 78 NC 127 NC 80 NC 129 VDD 82 VDD 131 DQ16 84 DQ48 133 DQ17 86 DQ49 135 DQ18 88 DQ50 137 DQ19 90 DQ51 139 VSS 92 VSS 141 DQ20 94 DQ52 143
PIN NAMES
Pin Name A0 ~ A11 BA0 ~ BA1 DQ0 ~ DQ63 CLK0 ~ CLK1 CS0 ~ CS1 RAS CAS WE DQM0 ~ 7 VDD VSS SDA SCL DU NC Function Address input (Multiplexed) Select bank Data input/output Clock input Chip select input Row address strobe Column address strobe Write enable DQM Power supply (3.3V) Ground Serial data I/O Serial clock Dont use No connection
CKE0 ~ CKE1 Clock enable input
61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93
* These pins are not used in this module. ** These pins should be NC in the system which does not support SPD.
* SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Rev. 0.0 April. 2000
M464S1724CT1
PIN CONFIGURATION DESCRIPTION
Pin CLK CS Name System clock Chip select Input Function Active on the positive going edge to sample all inputs.
PC100 SODIMM
Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. CKE should be enabled 1CLK+tSS prior to valid command. Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA11, Column address : CA0 ~ CA8 Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS, WE active. Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. (Byte masking) Data inputs/outputs are multiplexed on the same pins. Power and ground for the input buffers and the core logic.
CKE
Clock enable
A0 ~ A11 BA0 ~ BA1 RAS CAS WE DQM0 ~ 7 DQ0 ~
63
Address Bank select address Row address strobe Column address strobe Write enable Data input/output mask Data input/output Power supply/ground
VDD/VSS
Rev. 0.0 April. 2000
M464S1724CT1
FUNCTIONAL BLOCK DIAGRAM
CS1 CS0 DQM0 LDQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 UDQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CS LDQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 UDQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQM5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQM6 LDQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 UDQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CS LDQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 UDQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 SDRAM U0 ~ U7 SDRAM U0 ~ U7 SDRAM U0 ~ U7 SDRAM U0 ~ U7 SDRAM U0 ~ U3 SDRAM U4 ~ U7 10 DQn VDD Three 0.1 uF X7R 0603 Capacitors per each SDRAM Vss Note : Use a zero ohm jumper to isolate A12 from the SDRAM pins in non-256Mbit designs. To all SDRAMs Every DQ pin of SDRAM CLK0/1 SCL CS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQM7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 LDQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 UDQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
PC100 SODIMM
DQM4 LDQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 UDQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CS LDQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 UDQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CS
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQM2
U0
U4
U2
U6
CS
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 A0 ~ A11, BA0 & 1 RAS CAS WE CKE0 CKE1
U1
U5
U3
LDQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 UDQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
CS
U7
Serial PD
SA0 SA1 SA2
SDA WP
U0/U4 U1/U5 U2/U6 U3/U7
Rev. 0.0 April. 2000
M464S1724CT1
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to Vss Voltage on VDD supply relative to Vss Storage temperature Power dissipation Short circuit current Symbol VIN, VOUT VDD, VDDQ TSTG PD IOS Value -1.0 ~ 4.6 -1.0 ~ 4.6 -55 ~ +150 8 50
PC100 SODIMM
Unit V V C W mA
Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70C) Parameter Supply voltage Input high voltage Input low voltage Output high voltage Output low voltage Input leakage current Symbol VDD VIH VIL VOH VOL ILI Min 3.0 2.0 -0.3 2.4 -10 Typ 3.3 3.0 0 Max 3.6 VDDQ+0.3 0.8 0.4 10 Unit V V V V V uA 1 2 IOH = -2mA IOL = 2mA 3 Note
Notes : 1. VIH (max) = 5.6V AC.The overshoot voltage duration is 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is 3ns. 3. Any input 0V VIN VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
(VDD = 3.3V, TA = 23C, f = 1MHz, VREF = 1.4V 200 mV) Symbol CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 COUT Min 25 25 15 15 15 10 10 Max 45 45 25 21 25 12 12 Unit pF pF pF pF pF pF pF
Parameter Input capacitance (A0 ~ A11, BA0 ~ BA1) Input capacitance (RAS, CAS, WE) Input capacitance (CKE0 ~ CKE1) Input capacitance (CLK0 ~ CLK1) Input capacitance (CS0 ~ CS1) Input capacitance (DQM0 ~ DQM7) Data input/output capacitance (DQ0 ~ DQ63)
Rev. 0.0 April. 2000
M464S1724CT1
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70C) Parameter Symbol Burst length = 1 tRC tRC(min) IO = 0 mA CKE VIL(max), tCC = 10ns CKE & CLK VIL(max), tCC = CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable CKE VIL(max), tCC = 10ns CKE & CLK VIL(max), tCC = CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable IO = 0 mA Page burst 4Banks activated tCCD = 2CLKs tRC tRC(min) CKE 0.2V C L Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. Unless otherwise noted, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ) Test Condition
PC100 SODIMM
Version -1H -1L 680 8 8 160
Unit
Note
Operating current (One bank active) Precharge standby current in power-down mode
ICC1 ICC2P ICC2PS ICC2N
mA
1
mA
Precharge standby current in non power-down mode ICC2NS Active standby current in power-down mode ICC3P ICC3PS ICC3N ICC3NS
mA 56 40 40 240 160 mA mA
mA
Active standby current in non power-down mode (One bank active)
Operating current (Burst mode) Refresh current Self refresh current
ICC4
700
mA
1
ICC5 ICC6
960 12 6.4
mA mA mA
2
Rev. 0.0 April. 2000
M464S1724CT1
AC OPERATING TEST CONDITIONS (VDD = 3.3V 0.3V, TA = 0 to 70C)
Parameter AC input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition Value 2.4/0.4 1.4 tr/tf = 1/1 1.4 See Fig. 2
PC100 SODIMM
Unit V V ns V
3.3V
Vtt = 1.4V
1200 Output 870 50pF VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA Output Z0 = 50
50
50pF
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted) Parameter Row active to row active delay RAS to CAS delay Row precharge time Row active time Row cycle time Last data in to row precharge Last data in to Active delay Last data in to new col. address delay Last data in to burst stop Col. address to col. address delay Number of valid output data Symbol -1H tRRD(min) tRCD(min) tRP(min) tRAS(min) tRAS(max) tRC(min) tRDL(min) tDAL(min) tCDL(min) tBDL(min) tCCD(min) CAS latency=3 CAS latency=2 70 2 2 CLK + 20 ns 1 1 1 2 1 20 20 20 50 100 70 Version -1L 20 20 20 50 ns ns ns ns us ns CLK CLK CLK CLK ea 1 2,5 5 2 2 3 4 1 1 1 1 Unit Note
Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. 5. For -1H/1L, tRDL=1CLK and tDAL=1CLK+20ns is also supported . SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + 20ns.
Rev. 0.0 April. 2000
M464S1724CT1
AC CHARACTERISTICS (AC operating conditions unless otherwise noted) REFER TO THE INDIVIDUAL COMPONENT, NOT THE WHOLE MODULE.
Parameter CAS latency=3 CAS latency=2 CLK to valid output delay CAS latency=3 CAS latency=2 Output data hold time CLK high pulse width CLK low pulse width Input setup time Input hold time CLK to output in Low-Z CLK to output in Hi-Z CAS latency=3 CAS latency=2 CAS latency=3 CAS latency=2 tCH tCL tSS tSH tSLZ tSHZ tOH 3 3 3 3 2 1 1 6 6 tSAC Symbol Min CLK cycle time tCC 10 10 6 6 3 3 3 3 2 1 1 -1H Max 1000 Min 10 12
PC100 SODIMM
-1L Max 1000 6 7
Unit
Note
ns
1
ns
1,2
ns ns ns ns ns ns 6 7 ns
2 3 3 3 3 2
Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Rev. 0.0 April. 2000
M464S1724CT1
SIMPLIFIED TRUTH TABLE
Command Register Mode register set Auto refresh Refresh Entry Self refresh Exit L H H
CKEn-1 CKEn CS RAS CAS
PC100 SODIMM
(V=Valid, X=Dont care, H=Logic high, L=Logic low)
WE DQM BA0,1 A10/AP A11, A9 ~ A0 Note
H H
X H L H X X
L L L H
L L H X L H
L L H X H L
L H H X H H
X X
OP code X
1,2 3 3
X X X V V
X Row address L H
Column address (A0 ~ A8) Column address (A0 ~ A8)
3 3
Bank active & row addr. Read & column address Write & column address Burst stop Precharge Bank selection All banks Clock suspend or active power down Entry Exit Entry Precharge power down mode Exit DQM No operation command Auto precharge disable Auto precharge enable Auto precharge disable Auto precharge enable
L L
4 4,5 4 4,5 6
H H H
X X X
L L L H L
H H L X V X X H X V X
L H H X V X X H X V
L L L X V X X H X V
X X X
V
L H X
V X
L H
X
H L H
L H L
X X X X X X V X X 7
X H L
L H H
H
H L
X
H L
X H
X H
X H
X
Notes : 1. OP Code : Operand code A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 clock cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected. If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Rev. 0.0 April. 2000
M464S1724CT1
PACKAGE DIMENSIONS
PC100 SODIMM
Units : Inches (Millimeters)
2.66 (67.56) 2.50 (63.60) 0.16 0.039 (4.00 0.10) 0.79 (20.00) 0.24 (6.0) 2-R 0.078 Min (2.00 Min) 1.25 (31.75) 0.024 0.001 (0.600 0.050) 0.008 0.006 (0.200 0.150) 0.03 TYP (0.80 TYP)
1
59
61
143
0.13 (3.30)
0.91 (23.20)
0.10 (2.50)
0.18 (4.60) 0.083 (2.10)
1.29 (32.80)
2- 0.07 (1.80)
Z 0.15 (3.70)
2 60 62 144
Y
0.150 Max (3.80 Max) (3.20 Min) (4.00 Min) 0.125 Min 0.157 Min 0.16 0.0039 (4.00 0.10) 0.06 0.0039 (1.50 0.1)
0.04 0.0039 (1.00 0.10)
Detail Z
(2.540 Min)
0.100 Min
Detail Y
Tolerances : .006(.15) unless otherwise specified The used device is 8Mx16 SDRAM, TSOP SDRAM Part No. : K4S281632C
Rev. 0.0 April. 2000

▲Up To Search▲

Price & Availability of M464S1724CT1-L1LC1L

	To Download M464S1724CT1-L1LC1L Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .